One type of power MOSFET transistor is known as a vertical diffused MOS (VDMOS) transistor. A transistor of this type is described in U.S. Pat. No. 4,631,564 to J. M. S. Neilson et al., issued Dec. 23, 1986, entitled GATE SHIELD STRUCTURE FOR POWER MOS DEVICE, and herein incorporated by reference.
Various arrangements of field effect transistors are known from the background literature in the art, as illustrated by the following references, herein incorporated by reference.
Honda U.S. Pat. No. 4,394,590 teaches an invention for providing a series arrangement of field effect transistors, permitting high voltage operation of the same, wherein resistor/capacitor biasing circuits are utilized for permitting high frequency operation of the circuit. Zener diodes are included between the gate and source electrodes of the field effect transistors in order to provide protection by limiting the voltage that occurs between the electrodes to the zener voltage, which is chosen to be lower than the breakdown voltage between the gate and source electrodes.
O'Connor et al U.S. Pat. No. 4,590,395 teaches a circuit including an FET transistor for driving a bipolar transistor. A zener diode 42 is connected between the gate of the FET transistor and its common connection with a parallel resistor 41a and capacitor 41. The zener diode 42 provides a charging and discharging path between the bipolar transistor 38 and the speed-up capacitor 41, thereby providing rapid turn-on and turn-off of transistor 38.
Majumdar et al U.S. Pat. No. 4,672,245 discloses a high frequency power switching device including a MOSFET transistor 2 driving a bipolar transistor 3, with a circuit including the combination of a zener diode and two other diodes 7 and 8 connected between the gate electrode of the MOSFET 2 and the base electrode of the bipolar 3, for permitting a single driver to be used in turning the device on and off. The diodes permit the bipolar transistor to be operated in its non-saturated region, thereby reducing the storage time of bipolar transistor 3, while widening the reverse bias safe operating area for the same. In this manner, high operating speed under relatively high current and voltage conditions is obtained, thereby enhancing the frequency response of the device.
Ueno et al U.S. Pat. No. 4,801,983 teaches a unidirectionally switching circuit that includes Schottky diodes connected between the source and drain electrodes of field effect transistors incorporated in the switching circuit. The Schottky diodes are connected in a series circuit with their associated FET, for providing unidirectionally current flow, and substantially reducing charge storage effects for enhancing the switching operation of the circuit.
Cogan U.S. Pat. No. 4,811,065 teaches the combination of a Schottky diode with a vertical DMOS transistor on a common substrate. A cross section of the DMOS transistor is shown in FIG. 6, whereas the equivalent circuit thereof is shown in FIG. 7. Note that the Schottky diode is in effect connected in parallel across the body diode of the DMOS transistor, to prevent the body diode from becoming forward biased, thereby eliminating the recovery time required for the body diode to recover from a conductive or forward biased state to a non-conductive or reversed biased state. By using the Schottky diode in the manner for diverting current from flowing through the body diode during high dv/dt operating conditions, turn-on of the DMOS transistor is enhanced. The reason is that no minority carriers can flow into the PN body diode to recombine. Also, through use of the Schottky diode, the parasitic bipolar junction transistor formed by the source, body region, and drain of the DMOS transistor cannot turn on, thereby preventing secondary breakdown of the bipolar junction transistor. Also, FIG. 5 of this patent discloses a circuit that includes the use of external diodes in combination with a DMOS transistor to avoid unwanted dv/dt turn-on. As shown in FIG. 5, an external diode is connected in parallel with the DMOS transistor, and a low voltage Schottky diode is connected in series with the DMOS transistor. In this manner, only the parallel connected silicon diode conducts current, thereby diverting current from flowing through the body diode, avoiding the unwanted storage time caused by conduction of the current through the body diode.
Mihara U.S. Pat. No. 4,893,158 discloses an overvoltage protection circuit for a power MOSFET device. In various embodiments of the invention taught in this patent, such as those shown in FIGS. 28A, 29A, 30A, and 31A, zener diodes are included in the overvoltage protection circuits to provide the overvoltage protection function.
Steigerwald U.S. Pat. No. 4,967,109 discloses a gate driver circuit that includes an inductor 28 connected in the main current conduction path between two field effect transistors 14 and 16, whereby the input capacitance of the power switching device being driven, and the inductance 28 provide a resonance circuit during turn-on for increasing the gate voltage by about twice that of the voltage of the power supply connected to the driver transistors. A Schottky diode 30 is connected between the voltage supply V.sub.s and the FET 14, for preventing the input capacitance from discharging back into the power supply.
The design and fabrication of a vertical power MOSFET with an integral driver is described in a paper by Joseph B. Bernstein, entitled "DESIGN AND FABRICATION OF A VERTICAL POWER MOSFET WITH AN INTEGRAL DRIVER", Copyright by MIT, 1986.
In power devices generally of this type, built-in circuit functions may typically be provided, utilizing diodes, lateral bipolar transistors and lateral MOS devices having N+/P junctions formed from the N+ source and P body diffusions used for forming the standard power MOS device.
As is known, a parasitic vertical NPN transistor is also formed by the VDMOS structure; a drawback of this type of device is the reduction of dv/dt capability resulting from the high gain of the parasitic bipolar vertical NPN transistor. (Typically, the presence of this transistor does not pose a serious problem in standard VDMOS devices because the N+source diffusion is short circuited by a metal conductor connecting it to the P+ body region; the gain of the parasitic bipolar NPN transistor is thereby reduced and the dv/dt performance is thus not degraded.)